1. Field of the Invention
The present invention relates to an input/output interfacing circuit implemented in a semiconductor device, etc., and in particular it relates to an input/output interfacing circuit capable of inputting and outputting multiple values by a single signal line.
2. Description of the Related Art
Semiconductor devices such as a memory LSI, microprocessor, etc., are in the progress of high integration and high rate through the development of semiconductor manufacturing technology, wherein the data transfer rate has improved year by year.
In prior arts, in order to improve the data transfer rate, for example, in a memory LSI, a clock synchronizing type memory such as a synchronous DRAM, DDR SDRAM (Double Data Rate SDRAM), Rambus DRAM, etc., where an input/output circuit has improved operation speed has been developed. Also, the data transfer rate has been improved by increasing the number of bits of the input/output data to 16 or 32.
However, there is a limitation to heightening the operation speed of the input/output circuits. Also, an increase in the number of terminals increases the number of pads. Since the pad size depends on the packaging technology, it is difficult to shrink the size as semiconductor elements become finer. As a result, there is an undesirable possibility that the chip size is increased due to an increase in the number of pads. Hereafter, there is a possibility that the chip size is determined based on the number of pads. In a memory LSI, even if the number of address terminals is increased owing to the improvement of the integration level and an increase in the memory capacity, the chip size may be increased as described above.
As a way of improving the data transfer rate without an increase in the number of pads, that is, an increase in the chip size, a multiple value of data or addresses is taken into consideration.
FIG. 1 shows a multi-valued input/output circuit that the inventor has studied. The circuit shown in FIG. 1 is not publicly known.
In this type of multi-valued input/output circuit, a voltage generating unit 1 is formed in a semiconductor device at a transmitter that outputs data, and a plurality of voltage comparing units 2, a reference voltage generating unit 3 and a data restoring unit 4 are formed in a semiconductor device at a receiver that receives data.
The voltage generating unit 1 includes a data restoring unit 1a that decodes two-bit output data D1 and D0, a resistor part 1b that generates four types of voltages V4, V3, V2 and V1 by dividing resistance, and an output part 1c that outputs any one of the voltages V4 through V1 as an output voltage VOUT. The output part 1c is composed of a switch such as a CMOS transmission gate, etc. That is, the voltage generating unit 1 gives four types of output voltages VOUT to a semiconductor device at the receiver in response to the output data D1 and D0.
The respective voltage comparing units 2 compare the output voltages VOUT with the reference voltages VREF3.5, VREF2.5 and VREF1.5, respectively, accept the comparison results in synchronization with a clock signal CLK, and output the results as the input results RSL3, RSL2, and RSL1. The reference voltage generating unit 3 generates three types of reference voltages VREF3.5 through VREF1.5 by dividing the resistance. Herein, the reference voltage VREF3.5 is set between voltages V3 and V4, the reference voltage VREF2.5 is set between voltages V2 and V3, and the reference voltage VREF1.5 is set between voltages V1 and V2. That is, the figures at the end of these voltages show the relative values of voltages.
The data restoring units 4 receive the input results RSL3 through RSL1 and make any one of the input data IND3 through IND0 into a high level in accordance with the logic value of the output data D1 and D0.
FIG. 2 shows the detail of the voltage comparing unit 2.
The voltage comparing unit 2 includes a differential amplifier 5, a latching circuit 6, and an output circuit 7. The differential amplifier 5 has a current mirror circuit and changes the output node to a high level or low level in accordance with the output voltage VOUT and reference voltages VREF3.5 (or VREF2.5, VREF1.5). The latching circuit 6 accepts an output from the differential amplifier 5 in synchronization with a rise edge of a clock signal CLK. The output circuit 7 outputs data, which are latched by the latching circuit 6, as the input results RSL3 (or RSL2, RSL1).
FIG. 3 shows the detail of the data restoring unit 4.
In the data restoring unit 4, inverted logic of the input result RSL3 is outputted as input data IND3, inverted logic of the input result RSL2 is outputted as input data IND2 when the input result RSL3 is at a high level, and inverted logic of the input result RSL1 is outputted as input data IND1 when the input result RSL2 is at a high level, and the logic, which is the same as the input result RSL1, is outputted as input data IND0. As a result, for example, when both output data D1 and D0 are at a high level (xe2x80x9c3xe2x80x9d in the binary code), only the input data IND3 is made into a high level, and when the output data D1 and D0 are in a low level and high level (xe2x80x9c1xe2x80x9d in the binary code), respectively, only the input data IND1 is made into a high level.
As shown above, in the transmitter, any one of the voltages V4 through V1 divided in response to the output data D1 and D0 is selected and outputted as an output voltage VOUT. In the receiver, by obtaining the logic value corresponding to the output voltage VOUT, a multiple value (in this case, 2 bits) are transmitted and received.
However, the voltage generator unit 1 of the transmitter selects any one of a plurality of voltages V4 through V1, which are obtained by dividing the resistance, by a switch such as a CMOS transmission gate, etc., in response to the output data D1 and D0. The difference in voltage corresponding to the logic value is small because the voltages are generated by dividing the resistance. Therefore, it was difficult to change the output voltage VOUT to a high rate when switching the CMOS transmission gate, etc. Since the difference in voltage corresponding to the logic value is small, only two-bit of data could be made into a multiple value.
In addition, the voltage range in which the differential amplifier 5 effectively operates is predetermined in the receiver, which makes it difficult to actuate the differential amplifier 5 in all the ranges of the output voltages VOUT. As a result, the differential amplifiers 5 of the voltage comparing units 2 shown in FIG. 2 have to be designed so as to optimally operate in correspondence with the received output voltage VOUT, respectively.
It is therefore an object of the invention to provide an input/output interfacing circuit capable of inputting and outputting multiple value data at high speed by a simplified circuit, and a semiconductor device having the input/output interfacing circuit.
According to one of the aspects of the input/output interfacing circuit of the invention, the input/output interfacing circuit includes a current generating unit in the transmitter, and a reference current generating unit, a plurality of current comparing units, and a data restoring unit in the receiver. The current generating unit generates output currents respectively corresponding to each of logic values. The reference current generating unit generates a plurality of reference currents. The current comparing units respectively compare the reference currents with the output current from the transmitter. The data restoring unit restores the logic values in the receiver according to the comparison results from the current comparing units. That is, the current is varied in accordance with each of logic values (for example, data, address, etc.) that are transmitted from the transmitter to the receiver, and the logic value is restored in the receiver according to differences in the current values. In other words, changing values of the currents which flow in a signal line, enables transmission of multiple value information from the transmitter to the receiver.
By forming a plurality of current comparing units in the receiver, it is possible to easily, respectively compare the level of the output current from the transmitter with the levels of a plurality of reference currents. Further, it becomes possible to widen the operation range of the current comparing unit in comparison with prior art voltage comparing circuits. This eliminates necessity for fine adjustment of the current comparing unit in accordance with a value of an output current from the transmitter. That is, the design data of a plurality of current comparing units can be made the same.
It is possible to construct a high bit-rate multi-valued input/output interface by converting the logic value to the current value in the transmitter and restoring the logic value by comparing the intensity of the current in the receiver, compared with prior arts in which the voltage has been divided. In addition, in comparison with the prior arts in which the voltage has been divided, it is possible to easily increase the number of bits with a multiple value. As a result, the data transfer rate can be improved.
When the transmitter and the receiver are formed in separate devices, the number of input/output terminals (the number of pads) of devices can be decreased. The decrease in pad number results in reducing the chip size of both devices. In case where the transmitter and the receiver are formed in the same device, the number of signal line patterns that transmit logic values can be reduced. A reduction in layout size of the signal line patterns enables a reduction in chip size.
According to another aspect of the input/output interfacing circuit of the invention, the number of current comparing units and the number of reference currents generated by the reference current generating unit are set one smaller than the number the logic value could possibly be. Each of the reference current values is respectively set between the output current values adjacent thereto. Therefore, the number of the current comparing units can be minimized.
According to still another aspect of the input/output interfacing circuit of the invention, the transmitter and the receiver are respectively formed in separate devices. The input/output interfacing circuit includes a standard current generating unit in the transmitter, and a dummy current generating unit and a correcting circuit in the receiver. The standard current generating unit uses an element, which is identical to or equivalent to the element used in the current generating unit, and generates the standard current at the output. For example, the standard current generating unit generates the standard current at the output, which has the same value as the output current generated by the current generating unit corresponding to a logic value. The dummy current generating unit is constructed identically to or equivalently to the standard current generating unit, and generates standard current at the input. The correcting circuit controls the reference current generating unit to correct the reference current according to a difference between the standard current at the output and the standard current at the input.
The output current and the reference current that are compared by the current comparing unit are expected to intrinsically have a predetermined correlation. However, where the transmitter and receiver are formed in separate devices, the relationship between the output current and the reference current may change due to differences in power supply voltage, operating temperature, or production conditions of the respective devices. Since the standard current generating unit and the dummy current generating unit are formed identically to or equivalently to each other, the change creates a difference between the standard current at the output and the standard current at the input. Therefore, since the reference current is corrected according to the difference, it is possible to restore the logic value in the receiver with reliability.
According to further another aspect of the input/output interfacing circuit of the invention, the transmitter and the receiver are formed in separate devices. The input/output interfacing circuit includes, in the receiver, a current source that supplies a current to the current generating unit in the transmitter, and a current source that supplies a current to the reference current generating unit in the receiver. Therefore, the current supply capacities of both the current sources become identical to each other. As a result, the correlation between the output current and the reference current can be maintained with high accuracy.
According to yet another aspect of the input/output interfacing circuit of the invention, the current generating unit includes a plurality of transistors with drivability in different stages of strength. Each bit of the logic values, which are expressed in binary number is respectively supplied to the inputs of transistors. The output current is generated according to a value of current which flows in the transistors that are turned on in accordance with the logic values. Therefore, the logic values consisting of a plurality of bits can be easily converted to an output current.
According to yet another aspect of the input/output interfacing circuit of the invention, the current comparing unit compares the output current with the reference current in synchronization with a timing signal used in the transmitter. That is, the output current and reference current can be compared with each other with accuracy at a predetermined timing synchronized with the transmitter.
According to one of the aspects of the input/output interface of the invention, a transmitting device includes a current generating unit and a standard current generating unit, and the receiving device includes a reference current generating unit, a current comparing unit, a dummy current generating unit, and a correcting circuit. The current generating unit generates an output current corresponding to the logic value. The standard current generating unit generates the standard current at the output by using an element that is identical to or equivalent to the element used for the current generating unit. For example, the standard current generating unit generates standard current at the output having the same value as the output current that is generated by the current generating unit, corresponding to a logic value. The reference current generating unit generates reference currents. The current comparing unit respectively compares values of the reference currents and the output current. The dummy current generating unit is constructed identically to or equivalently to the standard current generating unit, and generates standard current at the input. The correcting circuit controls the reference current generating unit on the basis of a difference between the standard current at the output and the standard current at the input, thereby correcting the reference current values.
The output current and the reference current that are compared by the current comparing unit are expected to intrinsically have a predetermined correlation. However, where the transmitter and the receiver are formed in separate devices, the relationship between the output current and the reference current may change due to differences in power supply voltage, operating temperature, or production conditions of the respective devices. Since the standard current generating unit and the dummy current generating unit are formed identically to or equivalently to each other, the change leads to creating a difference between the standard current at the output and the standard current at the input. Therefore, since the reference current is corrected according to the difference, it is possible to reliably compare a value of the reference current and the output current.
According to one of the aspects of a semiconductor device having the input/output interfacing circuit of the invention, the input/output interfacing circuit includes a reference current generating unit, a plurality of current comparing units, and a data restoring unit. The reference current generating unit generates a plurality of reference currents. The current comparing units respectively compare the reference currents with the output currents in accordance with the logic value supplied from the exterior. In addition, the data restoring unit restores the logic value sent from the transmitter in the receiver according to the comparison results from the current comparing units. That is, the current is varied in accordance with the logic values (for example, data, address, etc.) that are transmitted from the transmitter to the receiver, the logic value is restored in the receiver according to a difference in the current values. In other words, changing values of the currents which flow in a signal line, enables transmission of multiple value information from the transmitter to the receiver.
Since a plurality of current comparing units are formed in the receiver, it is possible to easily compare values of the output current from the transmitter and a plurality of reference currents. It is also possible to further widen the operating range of the current comparing units, compared with a prior art voltage comparing unit. As a result, it is not necessary to fine adjust the current comparing units in accordance with the values of the output current from the transmitter. That is, the design data of a plurality of current comparing units can be made identical to each other.
For example, receiving multiple value data in correspondence with a current value from one input terminal allows a reduction in the number of input terminals (number of pads) of a semiconductor device. Accordingly, the reduction in pad number enables a reduction in the chip size of the devices.
According to another aspect of the semiconductor device having the input/output interfacing circuit of the invention, the input/output interfacing circuit includes a current generating unit having a plurality of transistors with drivability in different stages of strength. Each bit of the logic values, which are expressed in binary number, is supplied to the inputs of the transistors. The input/output interfacing circuit generates an output current, which is inputted to and outputted from the exterior, according to a value of current which flows in the transistors that are turned on in accordance with the logic values. Therefore, the logic values consisting of a plurality of bits can be easily converted to an output current and can be inputted to or outputted from the exterior.